1. Field of the Invention
The present invention relates to an improved process for the fabrication of circuit traces having contacts to improve contact dimensional quality and to reduce waste or "thiefage" of conductor material without increasing fabrication process complexity. More particularly, the improved process is suitable for fabrication of circuits including raised bump-type contacts for use in the testing, "burn-in" and characterization of semiconductor dies prior to permanent packaging.
2. State of the Art
Burn-in is a reliability test of a semiconductor device or, as referenced herein, of a die, including a plurality of such devices, to identify physical and electrical defects which would cause the die to fail to perform to specifications or to fail altogether before its normal life cycle is completed. Thus, the die is subjected to an initial heavy duty cycle which elicits latent silicon defects. The typical burn-in process consists of biasing the die against a circuit board or burn-in die substrate, wherein the die under test (DUT) is subjected to an elevated voltage load while in an oven at temperatures of between about 125-150.degree. C. for approximately 24-48 hours. It is desirable to not only conduct a burn-in test but to fully characterize the performance characteristics of a die prior to assembly and packaging. This is particularly desirable in the case of multi-die assemblies, or so-called multi-chip modules ("MCM's").
Test packages to receive individual dies and which permit all of the above-referenced types of testing are disclosed in U.S. Pat. No. 5,367,253 (the "'253 patent"), assigned to the assignee of the present invention and incorporated herein by this reference. The test packages of the '253 patent include intermediate substrates or boards interposed between the DUT and the test package itself. Such intermediate substrates afford the opportunity to test dice having different bond pad configurations, and to replace such substrates when the circuit traces thereon fail or are damaged or the bump-type contacts at the die ends of the circuit traces wear, deform or are otherwise damaged.
The prior art process for fabricating a flexible intermediate substrate of the type employed in burn-in test packages begins with a sheet of polyimide film 20, such as Kapton.TM., laminated to a sheet of copper foil 22 (see FIG. 2A). The exterior surfaces of both the polyimide film 20 and the copper foil 22 are coated with an appropriate resist material to form a polyimide-side resist 24 and a cooper-side resist 26 (FIG. 2B). The copper-side resist 26 is exposed with a superimposed mask and then etched to reveal the external surface of the copper foil 22 (FIG. 2C). The exposed portions of the copper foil 22 are then etched to define circuit traces 12 for the KGD intermediate test substrate (FIG. 2D), the circuit traces extending at their outer ends through necked-down tie bars 16 to a bus bar 14 (see FIG. 3). The remaining copper-side resist 26 is then stripped away and a second coat of copper-side resist material 27 is applied to again cover the entire exterior surface of the copper foil with KGD circuit traces 12 (FIG. 2E). The polyimide-side resist 24 is then exposed through a suitable mask and subsequently etched to selectively expose the polyimide film 20 (FIG. 2F). The polyimide film 20 is then itself etched to produce round vias 30 through the polyimide film 20 to the adjacent, inner surface of the circuit traces 12 (FIG. 2G). The locations of the vias 30 at the die ends of the circuit traces 12 correspond to the locations of the bond pads of the semiconductor die to be tested. The polyimide-side resist 24 is then stripped away (FIG. 2H) and a metal bump 32 is electrolytically plated through the polyimide via 30 onto the circuit traces 12 (FIG. 2I). The second copper-side resist material 27 is then stripped off to produce the substrate with bumped circuit traces (FIG. 2I).
However, as shown in FIG. 3, the prior art process of electrolytically plating the metal bumps 10 on the copper circuit traces 12 laminated to a sheet of polyimide film 20 requires a copper bus bar 14 comprising a cathode and tie bars 16 for completing a circuit to previously-formed circuit traces 12 for the deposition of bump 32 on the ends of the circuit traces 12 submerged in the plating solution. Thus, while necessary for forming bumps or contacts 10, the copper bus bar 14 and tie bars 16 must be removed by cutting along kerf line 18.
The copper bus bar 14 comprises a considerable amount of copper material which requires a recycling process if the copper is to be recovered. Furthermore, removal of the copper bus bar 14 is an extra and unwanted circuit fabrication step. Moreover, because the tie bars 16 are generally non-uniform in cross-sectional area, different current densities are experienced at the bump ends of the copper traces 12. The differences in current densities on each copper trace 12 result in the plated bumps 10 becoming non-uniform in diameter and thus height for a given plating time. The differences in bump diameter and height make uniform contact with the bond pads on a semiconductor die to be tested much more difficult. In general, as disclosed in the '253 patent, the connection between the semiconductor die and the test package is non-permanent, wherein the die is biased against the bump-like contacts with a spring or the like such that the bond pads on the semiconductor die contact the plated bumps 10. Thus, even minor variations between the plated bump 10 heights may result in one or more die bond pads falling to make contact with one or more plated bumps 10. This lack of contact will result in a portion of semiconductor die not being under a voltage load during the burn-in process and prohibits complete electrical testing and characterization of the die. As a result, if a latent silicon defect exists in this portion of the semiconductor device, the burn-in process will not detect the defect. In addition to the foregoing problem, it should be recognized that in many instances, the bond pads of the die are recessed below the surface level of a passivation layer on the active surface of the die to protect circuitry thereon. With the variations in height and diameter of existing bump-type contacts 10, it is difficult to mate the die and KGD traces electrically through bumps 10 without damaging the bond pads through application of excessive biasing force or damaging the passivation layer adjacent the bond pad periphery as the die is forced into contact with the varying diameter and height bumps.
Therefore, it would be advantageous to develop a process which forms plated bumps which are uniform in height and diameter. Further, it would be advantageous to develop a process which reduces the cost per circuit trace by the elimination of inherent material thiefage caused by the need for a bus bar and tie bars. Finally, another advantage is the elimination of the additional process step of removing the bus bar by sawing through the tie bars 16 to release the copper circuit traces 12 on polyimide film 20.